I am a second-year PhD student at University of Edinburgh (UoE), UK. I received my master's degree from Eindhoven University of Technology (TU/e), Netherlands, and my bachelor's degree from Hefei University of Technology (HFUT), China. My research focuses on digital hardware acceleration systems for large-scale AI models, with an emphasis on overcoming memory and computational bottlenecks through novel architectures. I am currently working on efficient hardware accelerators for LLMs, VLMs, and generative AI.
Open to opportunities: I am always interested in potential collaborations and open to research internship opportunities in both academia and industry. Please feel free to reach out via email.
Download my CV (Updated: May 2026)
News
- [2025.07] [Paper] Our work "BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics" was accepted by ASAP 2026 and selected for an oral presentation.
- [2026.04] I finished my first-year annual review.
- [2026.04] I presented a poster and gave a two-minute talk on Towards Scalable GenAI Hardware Architectures with a Design Space Exploration Framework at the School of Engineering Research Conference 2026.
- [2026.03] I served as a teaching assistant for the Mini ASIC-BASIC Workshop and delivered a tutorial on Digital ASIC Flow in GF-22nm.
- [2026.02] I completed my first tape-out, Bent-Pyramid Systolic Array, in TSMC-180nm and served as a demonstrator for Digital System Laboratory 4.
- [2025.11] I attended Europractice's Advanced Node Digital IC Implementation course and received the certificate.
- [2025.10] I joined MeMRISYS 2025 in Edinburgh as a volunteer and served as a demonstrator for Digital System Laboratory 3.
- [2025.09] [Conference] I presented my work "LinkBo: a Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications" at SOCC 2025 in Dubai, UAE.
- [2025.07] [Paper] Our work "LinkBo: a Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications" was accepted by SOCC 2025 and selected for an oral presentation.
- [2025.01] I started my PhD at the University of Edinburgh, supervised by Dr. Shady Agwa and Professor Themis Prodromakis.
- [2024.11] I finished my internship at NXP Semiconductors and successfully defended my master's thesis at TU/e with a score of 8.5/10. Committee members: Marc Geilen, Manil Dev Gomony, and Chengmin Li.
- [2024.09] I received a conditional PhD offer from the University of Edinburgh.
- [2024.03] Congratulations to Intrinsic ID on being acquired by Synopsys.
- [2024.03] I moved my master's thesis to NXP Semiconductors in Nijmegen, supervised by Kimmo Salo and Gustavo Naspolini.
- [2023.11] I started working remotely as an Oversea VC Intern at Linear Capital.
- [2023.10] I completed my internship at Intrinsic ID with a score of 8.5 and also started my neuromorphic hardware research at TU/e.
- [2023.07] I joined Intrinsic ID for a 3.5-month internship, supervised by Rui Wang, Roel Maes, and Manil Dev Gomony.
- [2022.09] I started my master's study at Eindhoven University of Technology (TU/e), The Netherlands.
- [2022.07] I graduated from Hefei University of Technology with a bachelor's degree, supervised by Zhenmin Li.
Publications
BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics
IEEE International International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2026
Accepted as Oral Presentation and short paper
In this work, we present BenDi, an energy-efficient quasi-stochastic systolic architecture for bioelectronic systems on the edge. BenDi leverages multiple levels of energy and power optimization, ranging from circuits to software quantization, including low supply voltage, the Bent-Pyramid data format for quasi-stochastic multiplication, the DiP systolic dataflow, and hardware-aware quantization, to handle CNNs with high accuracy on the edge within limited hardware budgets.
LinkBo: a Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications
IEEE International System-on-Chip Conference (SOCC), 2025
Accepted as Oral Presentation and Student Contest
Paper / Slides / Poster / ArXiv (Full Version) / Website
We propose LinkBo, a single-wire communication protocol with dedicated hardware architecture, designed to achieve low latency (50.4 us), high throughput (up to 7.5 Mbps @ 11 cm and 300 kbps @ 15 m), and robust priority-aware delivery.
Education
University of Edinburgh
PhD Student in Engineering
Advisors: Professor Themis Prodromakis and Dr. Shady Agwa
Research interest: Digital hardware accelerators for generative AI.
Eindhoven University of Technology
MSc Electrical Engineering, Electronic Systems Track
GPA: 7.8/10
Thesis: LinkBo: A Robust Low-Latency 1-Wire Protocol for Chip-to-Chip Communications (8.5/10)
Hefei University of Technology
Bachelor in Integrated Circuit Design and Integrated Systems
GPA: 83.1/100 (Top 22%)
Thesis: The Research and Implementation of Router for Packet-Connect-Circuit Network-on-chip
Experience
NXP Semiconductors
Digital Design Intern
Location: Nijmegen, The Netherlands
Supervisors: Kimmo Salo, Gustavo Naspolini, and Manil Dev Gomony
- A Robust Low-latency 1-wire Protocol for Chip-to-Chip Communications for PowerIC
Linear Capital
Oversea VC Intern
Location: China (Remote, part-time)
Mentor: Wei Xin, Songyan Huang
Intrinsic ID (acquired by Synopsys)
IP Modeling and Digital IC Design Intern
Location: Eindhoven, The Netherlands
Supervisors: Manil Dev Gomony, Rui Wang, and Roel Maes
- Focus on a trellis-based Reed-Muller codec on FPGA for PUF IP.
Honors and Awards
- IEEE CAS Student Travel Grant, SOCC 2025
- Undergraduate Scholarship, 2021/2022
Skill
- Professional: Verilog / SystemVerilog / VHDL, FPGA, Lint, Linux, Cadence tools (Xcelium, SimVision, Conformal Lint, Virtuoso, Genus, Innovus)
- Miscellaneous: Python, C/C++, SystemC, MATLAB / Simulink, LaTeX, CUDA, PyTorch, Perl / TCL / Shell, Git
- Language: Mandarin (native), English
