I am a Second-year PhD student at University of Edinburgh(UoE), UK. I got my Master degree from Eindhoven University of Technology(TU/e), Netherlands and my bachelor degree from Hefei University of Technology(HFUT), China. My research focuses on designing digital hardware acceleration systems for large-scale AI models using novel architectures, aiming to overcome memory and computational bottlenecks. My current focus is on advancing hardware accelerators for LLMs, VLMs, and generative AI to enable next-generation intelligent computing.

Here is my CV, and I am looking for possible research collaboration. If you are interested in me, please feel free to contact me at any time.

🔥 News

📝 Publications

SOCC 2025

LinkBo: a Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications

Bochen Ye(TU/e & NXP), Gustavo Naspolini (NXP), Kimmo Salo (NXP), Manil Dev Gomony (TU/e)

IEEE International System-on-Chip Conference (SOCC), 2025

Selected as Oral Presentation and Student Contest

Paper/Slides/Poster/ArXiv(Full Version)/Website

We propose LinkBo, a single-wire communication protocol with dedicated hardware architecture, designed to achieve low latency (50.4 µs), high throughput (up to 7.5 Mbps @ 11 cm and 300 kbps @ 15 m), and robust priority-aware delivery.

This poster presents an automated design space exploration framework for dataflow systolic GenAI accelerators, aiming to identify the optimal hardware architecture for diverse workloads under given resource budgets.

Slides/Poster/Website –>

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🏫 Educations

2025.01-Now, University of Edinburgh, United Kingdom

• PhD student of Engneering
• Advisors: Professor Themis Prodromakis and Dr. Shady Agwa
• Research interest: Digital Hardware Accelerator for Generative AI.

2022.09-2024.11, Eindhoven University of Technology, The Netherlands

• Msc.Eletrical Engneering(track:Electronic System)
• GPA: 7.8/10
• Relevant Course: Digital integrated circuit design, Embedded computer architecture, Electronic design automation, Applied combinatorial algorithms, Intelligent architectures(focus on DNN/Hardware co-design), Systems on silicon(focus on SoC backend), Neuro computation(focus on Neuromorphic computing).
• Thesis: LinkBo: A Robust Low-Latency 1-Wire Protocol for Chip-to-Chip Communications (8.5/10)

2018.09 - 2022.07, Hefei University of Technology, China

• Bachelor in Integrated Circuit Design and Integrated Systems
• GPA: 83.1/100 (TOP 22%)
• Relevant Course: Analysis and Design of Integrated Digital Circuit, Microprocessor architecture and design, Introduction to SoC design, Verilog HDL and FPGA implementation and so on.
• Thesis: The Research and Implementation of Router for Packet-Connect-Circuit Network-on-chip

💻 Internships

2024.03 - 2024.10, NXP Semidocutors, Nijmegen NL

• Digital Design Intern

  I am working in AA-APS, this thesis project supervised by Kimmo Salo(NXP), Gustavo Naspolini(NXP), and Manil Dev Gomony(Bell Lab & TU/e). My work as follow:

  • Define a custom 1-wire digital communication protocol between two ICs.
  • Develope high-level model in Simulink and test the channel model with parasitic parameter.
  • Develop and verify an IP module implementing the new communication protocol using SystemVerilog.
  • Use Cadence Xcelium to simulate, Cadence SimVision to see the wave, Cadence Conformal Lint to lint and DesignSync to verision control.
  • Build a prototype demonstrator with 2 FPGAs.

2023.11 - 2024.06, Linear Capital, China (Remote Part-time)

• Oversea VC Intern

  During my internship at Linear Capital, my responsibilities included:

  • Mapping overseas talent in the academic and industrial sectors, providing vital insights for project recruitment and business collaborations.
  • Conducting assessments for the commercialization and implementation of potential projects, analyzing market opportunities and risks to support investment decisions.
  • Participating in the planning and execution of early-stage investments, collaborating with startups to drive project success.

2023.07 - 2023.10, Intrinsic ID(Now acquired by Synopsys), Eindhoven NL

• IP Modeling and Digital IC Design Intern

  I worked in Research and Security Department(now SoC Security of Synopsys). This internship supervised by Manil Dev Gomony(Bell Lab & TU/e) and Rui Wang & Roel Maes(Intrinsic ID). My work as follow:

  • Study on a trellis-based Reed-Muller codec.(Algorithm)
  • Use Python modeling it as a digital IP module.(software)
  • Design the architecture of codec and implementation by VHDL.(harware)
  • Verify on Arty-z7 FPGA(zynq) with vivado and vitis.(Embeded System)
  • Under the 50MHz condition, after several improvements, the hardware resource consumption decreased from 938 LUTs to 843 LUTs. Meanwhile, the decoding latency reduced to 6 clock cycles, and continuous decoding became possible.

🎖 Honors and Awards

• IEEE CAS Student Travel Grant, SOCC 2025
• Unergraduate Scholarship 2021/2022

📖 Skill

• Professional: Verilog/SystemVerilog/VHDL · FPGA · Lint · Linux · Cadence Tool(Xcelium,SimVision,Conformal Lint,Virtuoso,Genus,Innovus)
• Miscellaneous: Python · C/C++ · SystemC · MATLAB/Simulink · LaTex · CUDA · Pytorch · Perl/TCL/Shell · Git
• Language: Mandarian(Native), English