LinkBo: A Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications
Abstract
Cost-effective embedded systems necessitate utilizing the single-wire communication protocol for inter-chip communication, thanks to its reduced pin count in comparison to the multi-wire I2C or SPI protocols. However, current single-wire protocols suffer from increased latency, restricted throughput, and lack of robustness. This paper presents LinkBo, an innovative single-wire protocol that offers reduced latency, enhanced throughput, and greater robustness with hardware-interrupt for variable-distance inter-chip communication. The LinkBo protocol-level guarantees that high-priority messages are delivered with an error detection feature in just 50.4 µs, surpassing current commercial options, 1-wire and UNI/O by at least 20X and 6.3X, respectively. In addition, we present the hardware architecture for this new protocol and its performance evaluation on a hardware platform consisting of two FPGAs. Our findings demonstrate that the protocol reliably supports wire lengths up to 15 meters with a data rate of 300 kbps, while reaching a maximum data rate of 7.5 Mbps over an 11 cm wire, providing reliable performance for varying inter-chip communication distances.
Motivation
As the number of interconnected chips increases, the total number of required pins for both SPI and I2C grows accordingly. In Fig left, the total number of communication pins required for SPI increases sharply while I2C exhibits a more linear growth. 16-pin package occupies only 40% of the area of a 20-pin package and incurs just 60% of the cost.
Protocol
Two priority LinkBo messages format. HP and LP messages have different SYNC and PAYLOAD fields, but share the same CRC and ACK fields. Only LP messages include a SIZE field. HP messages are always completed within 50 μs, whereas the duration of LP messages depends on the payload size. In PAYLOAD, one byte in LP message contain 8 Manchester bits. The re-synchronization process for Manchester code during the transmission. The depth of the red edge represents the severity of the error. For multi-device transmission, arbitration with Wired-AND logic and use address message for configuration.
Simulation and Hardware Architecture
Top left: Ideal LinkBo model and testbench. The testbench can send messages to any module and receive them from another module. Top right: Channel model with parasitic parameter. In this figure, the TX and RX serve as interface between LinkBo and channel. The inductance, resistance and capacitance simulate the real wire characteristics. Bottom left: (1) Top-level architecture. LinkBo module is part of digital system in each chip, consisting of synchronizer, TOP FSM, RX, TX, driver, and PSC(for both TX and RX). (2) Transmitter architecture. TX is responsible for sending any priority message. (3) Receiver architecture. The RX is responsible for receiving messages, synchronizing, and sending an acknowledgment (ACK) signal. (4) Driver architecture. Driver consists of one Manchester encoder (XOR gate) and 4 MUXes. Bottom right: FPGA test setup. Two FPGAs are connected via a single wire, sharing the same PL design. Buttons and switches are used for signal input, while LEDs display the transmitted and received data.
Results
Results from simulation and FPGA test.
Conference Presentation
29th September 2025, Dubai, United Arab Emirates. Bochen Ye presented our work at the 2025 IEEE 38th International System-on-Chip Conference (SOCC).
Student Contest Poster
BibTeX
@INPROCEEDINGS{linkbo,
author={Ye, Bochen and Naspolini, Gustavo and Salo, Kimmo and Gomony, Manil Dev},
booktitle={2025 IEEE 38th International System-on-Chip Conference (SOCC)},
title={LinkBo: A Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications},
year={2025},
volume={},
number={},
pages={1-6},
keywords={Meters;Protocols;Throughput;Hardware;Robustness;System-on-chip;Wire;Low latency communication;Field programmable gate arrays;Standards;single-wire protocol;serial interface;hardware design;FPGA;Chip-to-chip communication},
doi={10.1109/SOCC66126.2025.11235355}
}